Mathematics · Computer Organization and Architecture
A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of 1 without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at the same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There are no structural or data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, what is the speedup (rounded off to two decimal places) obtained by X2 over X1 in executing P?
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