Computer Science · Computer Organization and Architecture
A processor design team is analyzing the efficiency of instruction execution. They observe that instructions with variable lengths cause delays in decoding. Which type of architecture would minimize this issue?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
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- 1RISC✓
- 2CISC
- 3VLIW
- 4Stack-based
Correct answer
RISC
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