Computer · Digital Electronics
What is the primary problem associated with using SR Flip-Flops in design of synchronous counters?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
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- 1They cannot be triggered by edge-sensitive clock signals.
- 2They can enter an invalid/indeterminate state if both Set and Reset inputs are active simultaneously.✓
- 3SR flip-flops are intrinsically too slow for counting applications.
- 4The flip-flops do not respond to synchronous clock signals.
Correct answer
They can enter an invalid/indeterminate state if both Set and Reset inputs are active simultaneously.
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