Physics · Digital Electronics
What is the output behavior of an SR latch (or flip-flop) when both the Set (S) and Reset (R) inputs are held at logic 0?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
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- 1The output enters an invalid or forbidden state.
- 2The output remains unchanged (holds its previous state).✓
- 3The output is force-set to logic 1.
- 4The output is force-reset to logic 0.
Correct answer
The output remains unchanged (holds its previous state).
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