In Xilinx XC4000 FPGAs, which mode of operation allows the Configurable Logic Block (CLB) to produce two independent functions, each involving up to four variables?

When the two inputs of a 2-input NAND gate are tied together to form a single input A, the resulting circuit behaves as which logic gate?

A logic function is given by F = ABC + DE. You are allowed to use only two-input AND gates and NOT gates. How many minimum number of two-input AND gates and NOT gates are required to implement this function without inverting input variables?