Physics · Digital Electronics - TTL Gates
In an open-collector TTL NAND gate, when all inputs are connected to a HIGH voltage logic level, the output transistor saturates. What is the typical output voltage (VOL) at output Y?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
Share:
- 12.4 V
- 20.2 V✓
- 34.5 V
- 40.8 V
Correct answer
0.2 V
Download Single Question PDF
Save this question and verified answer as a clean study sheet with live clickable link.
👥
Share with Friends & Study Groups
Challenge your peer aspirants on WhatsApp or Telegram to solve this question!
Online Test Series
Start Free Mock Test →Preparing for Physics?
Practice full-length mock tests with real exam timers, instant score analysis, and all-India ranking.
Chapter Practice
Practice Digital Electronics - TTL Gates MCQs →Want more practice questions on Digital Electronics - TTL Gates?
Solve complete topic-wise tests with detailed solutions on GkGet.
Related Practice Questions
Recommended practice questions in Physics · Digital Electronics - TTL Gates