CPU में अंकगणितीय और तार्किक संचालन के परिणामों को अस्थायी रूप से संग्रहीत करने के लिए कौन सा रजिस्टर जिम्मेदार है?

How many 128 × 8 bit RAM chips are required to construct a 2048-byte memory capacity?

A two-way set associative cache memory uses blocks of four words each. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128 K × 32. How many bits are there in the Tag, Set, and Word fields of the address format?

The time delays of the four segments in a pipeline are as follows: t1 = 50 ns, t2 = 30 ns, t3 = 95 ns, and t4 = 45 ns. The interface delay time tr = 5 ns. How long will it take to complete 100 tasks in the pipeline?

Which of the following is/are CISC characteristic(s) in Computer Architecture? (i) Variable length instruction formats (ii) A large variety of addressing modes (iii) Single cycle instruction execution

A computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register part to specify one of 64 registers, and an address part. How many bits are there in the operation code?

Match List-I with List-II: List-I (Micro-operation Category) P. Register transfer micro-operation Q. Arithmetic micro-operation R. Logic micro-operation S. Shift micro-operation List-II (Symbolic Representation)1. R2 ← R1 ∨ R32. R1 ← ashl R13. P: R2 ← R14. R2 ← R1 + R3 Choose the correct answer from the options given below:

Match List-I with List-II: List-I (Operation) P. Instruction Fetch Q. ADD R. POP S. JZ List-II (Register Used)1. AX2. ZF3. IP4. SP Choose the correct answer from the codes given below:

Given below are two statements: Statement I: In RISC-based processors, generally microprogrammed control is used. Statement II: In CISC-based processors, instructions are of variable lengths. In light of the above statements, choose the most appropriate answer from the options given below: