Computer Science · Pipelining

Consider an unpipelined machine with 10 ns clock cycles which uses 4 cycles for ALU operations and branches, and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20%, and 40%, respectively. Due to clock skew and setup, a pipelined version of the machine adds a 1 ns overhead to the clock. How much speedup is observed in the instruction execution rate when the pipelined machine is used?