Mathematics · Computer Architecture
Consider a 5-stage pipelined processor with stage delays 5 ns, 8 ns, 4 ns, 6 ns, and 8 ns. The inter-stage buffer delay is 2 ns. While executing a large number of instructions without conflicts, what is the throughput of the pipeline in instructions per second?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
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- 11 × 108✓
- 21.25 × 108
- 30.8 × 108
- 40.5 × 108
Correct answer
1 × 108
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