Computer Science · Pipelining

Consider a 5-stage pipelined processor with instruction execution stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). The delay of each stage is 15 nsec. If there is an overhead (latch delay) of 2 nsec, what is the actual clock cycle time (Tp) of this pipelined machine?