Computer Science · Computer Organization and Architecture
A 4-stage pipeline has stage delays of 150, 120, 160, and 140 ns respectively. Interstage registers have a delay of 5 ns. Assuming a constant clocking rate, what is the total time required to process 1000 data items on this pipeline?
- 1590.5 μs
- 2120.5 μs
- 3165.5 μs✓
- 4160.5 ms
Correct answer
165.5 μs
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