Electronics Engineering · Digital Electronics
A 4-bit ripple counter is designed using negative-edge-triggered T flip-flops with T = 1 for all stages. If the output Q of each flip-flop is connected to the clock input (CLK) of the next stage, which of the following modifications will correctly convert it into a 4-bit ripple down counter?
Verified Solution4 OptionsUpdated: October 2026👁️1 View
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- 1Connect the complement output (Q') of each flip-flop to the clock input of the next stage✓
- 2Use the same circuit but change only the least significant flip-flop (LSB) to a positive-edge-triggered type while keeping all other flip-flops negative-edge-triggered
- 3Reverse the order of connection between the flip-flops (MSB to LSB)
- 4Replace all T flip-flops with D flip-flops having D = Q' and use the same clock connection as before
Correct answer
Connect the complement output (Q') of each flip-flop to the clock input of the next stage
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